FPGA Development Board - strange shift operation behavior

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Try this code out. I just modified it to add the reset and logic to store initial value.

        1,2,3,4: led <= (led << 1);

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Same result: 1,2,3,4 = 0;

With D-latch same result:

module led4_reg(
    input        clk, 
    input        rst, 
    output reg  led
);
parameter BASE_LED_SEQUENCE = 12'b000011101101;
reg  led_value;
reg  circle_count;
reg  count;
always @(posedge clk or negedge rst)
begin
    if (!rst) begin
        count <= 0;
        circle_count <= 0;
    end else begin
        count <= count + 1'b1;
        if (count == 1) begin    
            count <= 1'b0;
            circle_count <= circle_count + 1'b1;
        end
        if (circle_count == 12)
            circle_count <= 0;        
    end
end
always @(led) begin
    led_value <= led;
end
always @(circle_count or led_value)
begin
    case (circle_count)
        0: led <= BASE_LED_SEQUENCE;
        1,2,3,4: led <= (led_value << 1);
        5:  led <= 12'b110110100001;
        6:  led <= 12'b101101000011;
        7:  led <= 12'b011010000111;
        8:  led <= 12'b110100001110;
        9:  led <= 12'b101000011101;
        10: led <= 12'b010000111011;
        11: led <= 12'b100001110110;
        default: led <= 12'b000_000_000_000;
    endcase
end
endmodule

if I use:

        1,2,3,4: led <= led_value;

it will get previous data.