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I've got an error: Pin "name" is stuck at GND.
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You'll get that for logic like;
my_output <= '0';
I do that for unused outputs, and then ignore the warning.
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In my design, and in normal operation, this pin will be all the time at GND. But If there is a SEU at a bad place, there is a possibility it goes high, so it is usefull (because the purpose of this pin is to detect the SEU...)
My question is: is the program implement exactly the schematics, or does it detect this "error", and the do some optimization?
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I suspect it will optimize the logic and delete it.
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I've got an other warning just after saying that this pin does not drive any logic, so I'm a bit afraid that the system removed for optimization purpose this part of my design...
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Sounds like it.
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If yes, is it possible to force it to implement my design exactly? (I'm currently using the schematic editor to implement my design...)
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How about;
You have two pins; my_input and my_output.
my_output <= '0';
will generate the FPGA driven low value
my_input can be physically tied to my_output on the PCB (use two BGA pads that are right next to each other). Drive the my_input signal to your voting logic.
If you get a SEU in the my_output or my_input path, you'll detect it.
Cheers,
Dave
Honored Contributor
