Force a signal in the output of a logical gate: destructive?

There are some really good books on VHDL and Verilog that show how to do this, as well as many other basic functions. I recommend Ashenden's VHDL book and Thomas & Moorby's Verilog text, depending on which HDL you are using. Viirtually all FPGA I/Os have a tri-state function.

As Dave (above) indicates, there really isn't a good reason to have the I/O of your device in the wrong state - that's why we use programmable logic.

Enjoy the learning process - FPGAs can be really fun to work with.