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But I've got a SRAM behind the FPGA, so the loss of voltage caused by the R will weaken the signal, maybe to the point that the SRAM cannot decode it anymore, no?
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The SRAM input will be high-impedance (it won't draw much current), so worst-case the resistor will form an RC circuit with the pin capacitance of the SRAM pad/pin, and you'll get a slower clock rate.
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When you mean that I can limit the current, does that mean that the FPGA can handle some "reverse" current without burning?
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FPGA pins can source or sink current, eg., they can turn on an LED by either driving current through it, or sinking current to ground. So, as long as you keep your pin source/sink currents within specification, you are ok.
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By the way, i've got an other question. Is it possible to make a modified IO buffer so it act like this:
-> You can set the direction (input or output)
-> You can disable the output if in output mode (so, in output mode, it becomes a tristate gate)?
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Sure. Just create a tri-state;
data_pin <= (others => 'Z') when (data_oe = '0') else data_out;
You can always read the state of the pin via data_pin, and you will only ever drive the data_pin bus when data_oe is '1'. You just need to figure out what the logic you require for data_oe is.
Cheers,
Dave
Honored Contributor
