Force a signal in the output of a logical gate: destructive?

Thanks for your replie.

But I've got a SRAM behind the FPGA, so the loss of voltage caused by the R will weaken the signal, maybe to the point that the SRAM cannot decode it anymore, no?

When you mean that I can limit the current, does that mean that the FPGA can handle some "reverse" current without burning?

By the way, i've got an other question. Is it possible to make a modified IO buffer so it act like this:

-> You can set the direction (input or output)

-> You can disable the output if in output mode (so, in output mode, it becomes a tristate gate)?

Because when I see the block diagram of the output pad of the FPGA (ug_low_level.pdf), I really have the impression that it's possible. But the primitiv ALT_IOBUF seems to activate the input when it put the output buffer in high impedance.