For the input FPGA pin, can I configure the IO_STANDARD to "3.0-V LVTTL" if the signal comes at 3.3V level? Is it safe for FPGA I/O operation? Are any pros and cons of using "3.0-V LVTTL" I/O standard when signal is at 3.3V level?

Hi Anand!

I am using MAX10 device.

These FPGA pins are used to interface with a data bus, which is shared between multiple ICs on the PCB; because of that there are some extra stray capacitance present, so extra current capabilities might be desirable.

I think using 3.0-V-LVTTL I/O standard has more Current Strength capabilities (4 mA, 8 mA, 12 mA, 16 mA, Max) vs. 3.3-V-LVTTL (4 mA, 8 mA, Max). Do you agree?

Do you know to what value Max corresponds to?

When we talked about PCI-clamp diode. What is PCI stands for?

Thank you,

Andrey