For the input FPGA pin, can I configure the IO_STANDARD to "3.0-V LVTTL" if the signal comes at 3.3V level? Is it safe for FPGA I/O operation? Are any pros and cons of using "3.0-V LVTTL" I/O standard when signal is at 3.3V level?

Hi,

Why can't we use IO_STANDARD to "3.3-V LVTTL" ???

which device are you using?

1. Yes, you can use it(check respective device datasheet). but you have Apply series termination or enables the PCI-clamp diode(by default its ON). refer an447 https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an447.pdf
2. Diode clamped voltage can still exceed the maximum DC and AC specifications due to the high VCCIO voltage level of the bank in which the I/O resides. You must manage the voltage overshoot. You can leave the diode enabled without concern for the DC current as the I/O pin is not overdriven.

Regards

Anand