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Altera_Forum's avatar
Altera_Forum
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13 years ago

for module 'cpu' did NOT run successfully.

hello

I tried to create a new component with the SOPC Builder, this component is in the form of a verilog file "rtp_tx.v" which must have two interface, avalon master interface to connect with ddr sdram interface and avalon Slave connect with the cpu. but when I added the avalon master interface always displays errors. So I added another component in verilog avalon master, and the component rtp_tx.v I add a single interface avalon slave that I connect with the avalon master interface component avalon master and I connect 'avalon master interface to interface Slave ddr sdram.

it works and the generation is succesfull, but there's always this error

ERROR:slave data width (26) for slave avalon_master_0/avalon_slave_0 unexpected           Error: Generator program                  for module 'cpu' did NOT run successfully.

I do not know if what I did is correct or not because I am a beginner in this field

9 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    As the error message suggests you have a weird size for your data vector (26 bits). The supported data sizes are 8,16, 32, 64, 128, 256, 512 or 1024 bits

  • Altera_Forum's avatar
    Altera_Forum
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    edit your verilog file. You'll probably have to re-run the component editor too, to have it pick up the new vector size.

  • Altera_Forum's avatar
    Altera_Forum
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    Nut in my verilog file i defined "data input [31:0] payload_in_data;" it alredy 32 bit

  • Altera_Forum's avatar
    Altera_Forum
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    Okay, in that case check the signals used for the different interfaces in the component editor. You are probably using the wrong signal as readdata or writedata. Maybe an address vector instead of data?

  • Altera_Forum's avatar
    Altera_Forum
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    Hi

    i chek the signals used for different interface,I noticed that there's an address with widhth is 26 bits, my data is 32 bits widhth

    what can i do in this case ??

    thank you