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Altera_Forum's avatar
Altera_Forum
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13 years ago

for module 'cpu' did NOT run successfully.

hello I tried to create a new component with the SOPC Builder, this component is in the form of a verilog file "rtp_tx.v" which must have two interface, avalon master interface to connect wi...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Okay, in that case check the signals used for the different interfaces in the component editor. You are probably using the wrong signal as readdata or writedata. Maybe an address vector instead of data?