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Altera_Forum's avatar
Altera_Forum
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15 years ago

Fmax is small, please, help me to improve it!

Hi, in my small systemverilog project (about 1000 lines) I have one module that is critical to the performance (I attached it below). This module takes 4x16 bit words (In) per clock (Clk),...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Josyb,

thank you for your kind suggestions. You was right, this long bit operations near to DSP multipliers make large instability. I tried to make it pipelined as you told, but it was only small improvement, however, when I demux my result (Sum) and compute ScalX<=ScalX+Sum2-(ScalX>>>SHR) with half frequency, everything was ok, I succeed to achieve 406MHz with N=24 (384 multipliers) and very large (56 bit ScalX).

Thank you for your kind advice!

Sincerely,

Ilgis