Honored ContributorHi there.
I have DSP code in C with floating point, now I try to convert to FPGA to use fixed point. Can you guys show me how to do it? I did little research document from http://www.vhdl.org/fphdl/ with fixed_pkg_c.vhdl. But I don't know how to start. example in C: i_sample = 0.7071; q_sample = 0.2487; How do I take this floating point to convert to fixed point or hex value? Thank you guys, Sean
Honored Contributoryou need to scale according to your target range. If a signal is swinging say +/-1 then to scale it for 10 bit signed you need the max value of 1 = 511 and so on:
value = round(511*signal/max(abs(signal))); You may go lower for any other reason.Honored ContributorThanks kaz,
How do you convert that to verilog. Is there a module to take in float to convert to hex or fixed point? megafunction? SeanHonored ContributorIn terms of a general tool that converts C to verilog I never use them. You will need to do the conversion per the range(s) of your targets and aoid under/over representation. Conversion itself is very easy but the difficulty is knowing what the C code is doing.
Honored ContributorAltera has IP to convert float <> fixed:
http://www.altera.com/literature/ug/ug_altfp_mfug.pdfHonored ContributorThanks thepancake,
ALTFP_CONVERT? DSP C code has alot of floating point. I tried to convert DQPSK from C in FPGA for my research experiment. BTW, do you have sample for ALTFP_CONVERT module? SeanHonored ContributorOk. I got these errors message when I run modelsim of ALTFP_CONVERT.
Instantiation of 'lpm_add_sub' failed. The design unit was not found. Instantiation of 'lpm_compare' failed. The design unit was not found. Does anybody know how to fix this in modelsim? SeanHonored ContributorYou wanted to convert values from DSP C code to Verilog. I believe pancake misunderstood your requirement. I ca not imagine how an ip will be inserted between C and fpga. The ip is meant to take inputs in fpga and produce outputs in fpgas. I hope I am wrong but the ip solution is totally pointless for your task.
Honored Contributoryou need to add the lpm libraries to modelsim. Modelsim Altera should have them already included.
The fixed package you're talking about is a great package to use when you've got values in fixed point. It can get confusing tracking integer and fractional bits in an integer. (like kaz says, you represent 0 to 1 with 0 to 511, but all bits are fractional). The fixed package allows you declare types that take care of the integer and fractional bits for you, so for the above example, the VHDL is difference, but the logic in the FPGA is identical: in "integer" form: signal my_fixed : unsigned(9 downto 0); my_fixed <= input + 256; --256 = 0.5 in 10 bit fixed point of range 0 to 1; alternatively: signal my_fixed : ufixed(-1 downto -10); my_fixed <= input + to_ufixed(0.5, -1, -10); --It makes code SOO much easier to read. But if all your inputs are floating point, you will need the float->fixed altera IP block. But once you've got the output from that you can work with the fixed point libraryHonored ContributorThanks kaz,
Yeah, we would like to move DSP C code to verilog. Most DSP code was written in C (pointers & floating point). I can use SystemVerilog (real) type, so I can see my data in modelsim. But my goal is to verilog only, Can I do it? SystemVerilog: real preamble_p[64]; // Works great Verilog: wire signed [31:0] preamble_p[64]; ???????Honored ContributorThanks Tricky,
Most of DSP code inputs are floating point. I'm not good with vhdl code, so could you interupted to verilog in your sample. Sean
