FLEX10k10 - Optimizing register to pin delay

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Howdy Folks!

So now that I've fixed my previous problem and got things working, I noticed a rather high register to pin delay. I've set optimization to 'speed' but I'm kinda shocked to see ~23ns been blown on getting from a to b.

My design drives about 12 different addresses through a case statement as well as hi-z when it's off the bus. Would using combinatorials be faster? The state machine isn't all that complicated, with about 30-odd states, most of them wait-states :-)

Suggestions welcome!

-Mux

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It is not clear from your post what your actual problem is. If it is reg to pin(and I assume it is) then try fast io ouput register.

Combinatorial approach implies pin to pin delay. In a standard fpga design e.g. with state machine you can't choose between RTL approach and combinatorial approach.

It might help to know why are you worried about this delay? after all everything in life is delayed!

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I noticed a rather high register to pin delay. I've set optimization to 'speed' but I'm kinda shocked to see ~23ns been blown on getting from a to b.

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You need to use Classic Timing Analyzer and timing constraints, eg., here's an example for a PLX PCI9054 PCI-to-Local Bus local bus interface;

#  PLX A/D bus input/output
set_instance_assignment 
	-name TSU_REQUIREMENT     "6.0 ns" -from clk -to plx_ad
set_instance_assignment 
	-name TH_REQUIREMENT      "1.0 ns" -from clk -to plx_ad
set_instance_assignment 
	-name TCO_REQUIREMENT     "9.0 ns" -from clk -to plx_ad
set_instance_assignment 
	-name MIN_TCO_REQUIREMENT "0.0 ns" -from clk -to plx_ad
#  PLX A/D bus control signal inputs
set_instance_assignment 
	-name TSU_REQUIREMENT "6.0 ns" -from clk -to plx_adsN
set_instance_assignment 
	-name TH_REQUIREMENT  "1.0 ns" -from clk -to plx_adsN
set_instance_assignment 
	-name TSU_REQUIREMENT "6.0 ns" -from clk -to plx_wr_rdN
set_instance_assignment 
	-name TH_REQUIREMENT  "1.0 ns" -from clk -to plx_wr_rdN
set_instance_assignment 
	-name TSU_REQUIREMENT "6.0 ns" -from clk -to plx_lastN
set_instance_assignment 
	-name TH_REQUIREMENT  "1.0 ns" -from clk -to plx_lastN
set_instance_assignment 
	-name TSU_REQUIREMENT "6.0 ns" -from clk -to plx_waitN
set_instance_assignment 
	-name TH_REQUIREMENT  "1.0 ns" -from clk -to plx_waitN
set_instance_assignment 
	-name TSU_REQUIREMENT "6.0 ns" -from clk -to plx_hold
set_instance_assignment 
	-name TH_REQUIREMENT  "1.0 ns" -from clk -to plx_hold
set_instance_assignment 
	-name TSU_REQUIREMENT "6.0 ns" -from clk -to plx_beN
set_instance_assignment 
	-name TH_REQUIREMENT  "1.0 ns" -from clk -to plx_beN
#  PLX A/D bus control signal outputs
set_instance_assignment 
	-name TCO_REQUIREMENT     "9.0 ns" -from clk -to plx_rdyN
set_instance_assignment 
	-name MIN_TCO_REQUIREMENT "0.0 ns" -from clk -to plx_rdyN
set_instance_assignment 
	-name TCO_REQUIREMENT     "9.0 ns" -from clk -to plx_termN
set_instance_assignment 
	-name MIN_TCO_REQUIREMENT "0.0 ns" -from clk -to plx_termN
set_instance_assignment 
	-name TCO_REQUIREMENT     "9.0 ns" -from clk -to plx_dp
set_instance_assignment 
	-name MIN_TCO_REQUIREMENT "0.0 ns" -from clk -to plx_dp
set_instance_assignment 
	-name TCO_REQUIREMENT     "9.0 ns" -from clk -to plx_hold_ack
set_instance_assignment 
	-name MIN_TCO_REQUIREMENT "0.0 ns" -from clk -to plx_hold_ack

These parameters were tweaked until timing passed. If you can use IOE registers in your design, then you can also try setting FAST_INPUT_REGISTER and FAST_OUTPUT_REGISTER to on (there might be a fast output-enable register option too).

Rather than simply writing code, draw a block diagram and see where you can push the registers to. For example, if you included input registers and delayed the inputs by one clock, would it matter?

Read the plx_interface.pdf document here:

http://www.alteraforum.com/forum/showthread.php?t=34523&p=142651#post142651

Perhaps you can do something similar.

Cheers,

Dave

Thanks guys! I'll have a look...

FWIW, my state machine basically issues a bus request and then puts multiple different addresses on the bus. While the state machine is synchronous, the address case select is combinatorial. The longest (non-pin) delays stem from the fact that my outgoing CS is based on some of the address bits, so you'll get a bunch of multiplexers followed by yet another set of multiplexers / gates to figure out which CS to assert.

This one example that I managed to get down somewhat was somewhere around 36ns, with a whopping 20-odd ns going from the block to the output pin. I got around some of the initial timing problems by inserting wait-states (not pretty, wastes performance) but at least got that to work. It's a stop-gap but it'll do :-)

Last hurdle now is dealing with interrupts but that's a whole different story...

Cheers!

-Mux (ironic, I know)