Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Flash Memory VHDL. Write Duration. JEDEC.

Hello, I am using a flash memory amd29lv320d. It is CFI compliant. I designed a code for write, read and erase the flash in VHDL. For read and erase I have what I expected (talking in term...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Hello,

I decided to attach some image of the signals that I am generating from VHDL, maybe someone has already designed a driver for a Flash and can see something strange.

It is a standard FLASH, CFI jedec.

You can see the signal I_busy is the flag RY/BY that comes from the flash but takes too long time to be asserted.

Any sugerence will be apreciated.

Thank you.:cool: