fixed-point tips

The new VHDL floating point packages actually have all necessary means for typical DSP problems as in your example. But I used my own functions for scaling of products similar to the one you discussed above up to now. I didn't even try, if they synthesize with Quartus without problems. Basically, the method works for arbitrary fixed point and fractional numbers, if you use a variable shift factor in product scaling and additional saturation logic.

I show an example of a multiply with scaling and saturation for reference:

FUNCTION MUL_ASL (X1,X2: SIGNED; N: INTEGER) RETURN SIGNED IS
 VARIABLE P:SIGNED(X1'length+X2'length-1 downto 0);
 BEGIN
   P:=X1*X2;
   IF P(P'left-1 downto P'left-N) /= 0 AND P>=0 THEN
    P:= (others => '1');
    P(P'left-N):='0';
   ELSIF P(P'left-1 downto P'left-N) /= -1 AND P<0 THEN
    P:= (others => '0');
    P(P'left-N):='1';
   END IF;	
-- Result length equals X2
  RETURN P(P'left-N downto X1'length-N);
 END;

For fractional signed numbers with a -1..1 range, the shift factor has to be set to 1 to remove the double sign bit.

Fast parallel division as lpm_divide is consuming a lot of resources. It can't be avoided sometimes, but in many cases other solution can be found. For "slow" division applications, I generally use a serial divider, that needs one clock cycle per result bit. Another options is a 1/x look-up table.