Forum Discussion
Altera_Forum
Honored Contributor
14 years agoVHDL has divide, but its not really that useful for real designs because divides need some serious pipelining. So you need an IP divider instead that you can get in VHDL or verilog.
VHDL has divide, but its not really that useful for real designs because divides need some serious pipelining. So you need an IP divider instead that you can get in VHDL or verilog.