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Altera_Forum
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16 years ago

fixed point in verilog

hi. I understand that the fixed point in verilog is represented by signed [4:-2] where -2(2 bit for post binary point) is for tracking purpose. Pls correct me if i am wrong. However, i have n...
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Altera_Forum
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16 years ago

Verilog does not have special support for fixed point arithmetic. Using negative indexes is a nice way to remember how many fractional bits you have, but Verilog does not track it for you.

Since your inputs have only 1 fractional bit, your resolution is 0.5. You can't represent 3.25 or -6.125. You can only represent 3.0 or 3.5 or -6.0 and -6.5.

Aditionally, your output has 2 fractional bits. That is why you're seeing half of what you expect.