fixed point in verilog

Verilog does not have special support for fixed point arithmetic. Using negative indexes is a nice way to remember how many fractional bits you have, but Verilog does not track it for you.

Since your inputs have only 1 fractional bit, your resolution is 0.5. You can't represent 3.25 or -6.125. You can only represent 3.0 or 3.5 or -6.0 and -6.5.

Aditionally, your output has 2 fractional bits. That is why you're seeing half of what you expect.