Fitter error for fPLL from adjacent bank!

Hi,

You may get this error in the Quartus® Prime software for your based design if you are driving an fPLL and further user logic from the same reference clock pin.

Resolution To avoid this error insert a Clock Control Block (ALTCLKCTRL) Megafunction between the reference clock pin and both the fPLL and the user logic. For further information on using this IP, refer to Clock Control Block (ALTCLKCTRL) Megafunction User Guide (PDF)

Let me know if that is helpful.

Regards,

Wincent_Intel