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KHayes's avatar
KHayes
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3 years ago

FIT/MTBF data for MAX II CPLD (EPM570)

Hello,

For our risk analysis in the next iteration of our product, I'm looking for FIT/MTBF data for the MAX II CPLD (EPM570: Intel product page ) currently used.

Thanks for the data!

- Kyle

1 Reply

  • Zawani_M_Intel's avatar
    Zawani_M_Intel
    Icon for Frequent Contributor rankFrequent Contributor
    3 years ago

    Hello KHayes,


    Thank you for contacting Intel FPGA Community Forum.


    The FIT (Failure in Time) is the measure of failure rate in 109 device hours; e. g. 1 FIT = 1 failure in 109 device hours.

    For Intel FPGA and CPLD, failure rate is calculated based on the process technology, by extrapolating High Temperature Operating Life (HTOL) stress test results of that process technology to the use conditions.

    In the case of EPM570, it is belong to the Max II family (0.18um process technology), and have the same FIT rates at 25oC and 85oC.


    FIT rates for Max II products :

    FIT at 25oC (CL=60%) is 0.033 FITs

    FIT at 85oC (CL=60%) is 19 FITs


    Thank you!


    Wani