Forum Discussion
FIR II core IP outputs incorrect data.
- 5 years ago
Hi,
Would you mind to help opening a new thread on this. Thank you very much.
Hi,
Sorry for the delay. As I understand it from your screenshot, seems like the source data = undefined in your simulation. Sorry as I am not very familiar with VHDL and could not really further edit your test bench for testing.
To facilitate your debugging, I have generated a simple simulation example from the IP with 16 bits coeff and 16 bits input signed data using A10 in Q17.0Std. There seems to be no FIR .qsys file in your .rar, and thus I am using some dummy setting in my example. You may refer to the fir0.qsys in the test.zip. I have edited the test bench to feed constant data. From the Modelsim simulation, seems like I am able to get valid output from the IP as shown in the screenshot.
I have attached the ZIP of the simulation folder. You can run the simulation by doing the following:
1. Change directory in Modelsim to \test\fir0_tb\fir0_tb\sim\mentor\
2. Type "source msim_setup.tcl"
3. Type "ld" to compile
4. Type "do wave.do" to populate the waveform
5. Type "run -all" to run the simulation
You may further customize from this example with your input data as well as target configuration.
Please let me know if there is any concern. Thank you.
Best regards,
Chee Pin
Hello again
Thanks for your respose. I am going to look into it, but there is something that's confusing me about the results. The output is 7.5MSPS instead of 15 MSPS. Isn't it wrong. What am I missing here?
The reasons there is no qsys file is that I use the IP catalog directly. Should I use plaform designed instead?
Thanks.