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Altera_Forum's avatar
Altera_Forum
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12 years ago

FIR Compiler II multichannel operation

Hi all.

I'm using FIR compiler II megafunction to create a block with the following parameters:

Decimation filter this N = 2;

Number of channels : 11;

Clock frequency : 50 MHz;

Input sample rate : 0.12 MHz;

I have got new input ports: ast_sink_sop and ast_sink_eop.

Sometimes i want to send data only to the channel number 1 and don't use other channels.

How can I do it?

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  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    --- Quote Start ---

    I didn't describe the problem, my fault.

    I have 11 fir filters connected in series, each with decimation factor = 2, clock frequence = 120 kHz,same coefficients and different input sample rates (because of the decimation):

    1. 120 kHz

    2. 60 kHz

    3. 30 kHz

    4. 15 kHz

    5. 7500 Hz

    6. 3750 Hz

    7. 1875 Hz

    8. 937,5 Hz

    9. 468,75 Hz

    10. 234,375 Hz

    11. 117,1875 kHz

    It's working, but can't fit in our FPGA, even in case of increasing clock frequence.

    Thats why I want to do it with one filter and 11 channels.

    So, I want to use this channels with different frequences.

    I hope I explained the problem clear. What do you think about it?

    --- Quote End ---

    if your sampling rate is halved each time then you can't use multichannel as it expects one sample rate.

    You can decimate in a cascade but filters need not be identical as that is a waste of resource.

    you can reduce the burden on cutoff point as you go down the cascade. Alternatively you can decimate in one filter and that will also reduce resource due to decimation effect internally.
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    At these rates, unless you have a huge number of taps, you might just be able to do this in software with a fast Nios (with a hardware multiplier). By interleaving the FIR sequences, the top bandwidth uses 1 in 2 sequences, the next 1 in 4 and so on, you can fit in an infinite number of decimations - each decimation of course needs its own set of sample memory registers. However, you need them even if it is all done in hardware.

    As Kaz points out, if you do use the FIR blocks, only the last in the chain needs all those taps.