FIR Compiler II multichannel operation

At these rates, unless you have a huge number of taps, you might just be able to do this in software with a fast Nios (with a hardware multiplier). By interleaving the FIR sequences, the top bandwidth uses 1 in 2 sequences, the next 1 in 4 and so on, you can fit in an infinite number of decimations - each decimation of course needs its own set of sample memory registers. However, you need them even if it is all done in hardware.