Final year project question, PCIe interface to GPIO?

Okay thanks for letting us know before we started.

The USB 3.0 connection is interesting, we will explore the idea.

The data rate we need to achieve is variable however the more the merrier. We have a design that requires 128 bits to be read from the host every clock cycle for every computational core that we have and we plan to run the fpga at 100Mhz. that equates to 128Mb/s/core. For starters we will be impleming one core as a proof of concept so the 1GbE is entirely sufficient however once that is running we were hoping to make multiple cores. the 1GbE will limit us to 8 cores before we run into data starvation. Ideally we would like more than 8 cores which is why we were looking to explore other options.

Thanks for your reply,

Dmitry