Fifo interfacing problems, avalon

Trying to interface a dual clock FIFO with the avalon interface. Here is my setup so far...

fifo_read_req <- ava_read

fifo_read_clk <- ava_clk (50Mhz)

fifo_rdclk <= ava_clk;

fifo_read_req <= ava_read AND (NOT fifo_empty);

ava_data <= fifo_data;

ava_dataavailable_n <= fifo_empty;

ava_waitrequest <= ava_read AND fifo_empty;

The fifo is a dualclock 8 bit in 32 bit out 32kB showahead fifo.

The data in is of 40Mhz 1280*1024 Bytes...

When I create a DMA transfer from the FIFO to the ddr, the dma finish before all the data has reached the fifo! Thus reading when the fifo is empty :(

Please help!

Anyone have an idea?

Best Regards Claes