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Avichay's avatar
Avichay
Icon for New Contributor rankNew Contributor
3 years ago

FGT Refclk to Xcievers AGFB027R24C2E2VR0

Hi 1. The AGFB027R24C2E2VR0 datasheet requires LVDS reference clock input . see pic from the datasheet Table 66 , but the Evaluation board DK-DEV-AGF027F1ES schematics ,shows its ...
Ash_R_Intel's avatar
Ash_R_Intel
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hi,

The dev kit uses the pins that you show in the screenshot for CXL interface (which is based on PCIe) and uses the HCSL IO standard which is nearer to the LVPECL interface.

However, if you use this F-tile for some other interface, recommend you to follow the datasheet and assign LVDS.

The decision should be based on the data rate, interface recommendation and power consumption. There are many references on internet to each of the type of interface.


Regards