Fast Input Register Logic Option

You need to implement a clock multiplexer (altclkctrl or something like that). That way the I/O registers only see one clock, but that clock is the output of a clock mux.

What device? I assume you're oversampling, and therefore need all 4 phases capturing simultaneously? Could you use a PLL and make a 4x clock that drives the input register? If not, you'll really want to hand-place the registers. What's going to hurt you is that you can only get 2 clocks into a LAB(varies with device, but I don't think any allow 4) and so you can't put all 4 registers in the same LAB right next to the I/O. The fitter will naturally put two right next to it and the other 2 a LAB away, which makes for bad skew. You'll want to place the 4 into LABs equidistant away, such as 2 in the LAB diagonally away from the I/O and the other 2 on the other diagonal(it depends which edge you're on for me to say what diagonal). You're then still at the mercy of the router doing the same thing to each register. I've done this before but it's not easy. You might want to put the structure in a partition so that you can lock down the placement and routing when you get something you want.

@dwh@ovro.caltech.edu: I am using stratix IV device. Are u sure this will allow fitter to place fast input registers. Right know I am feeding a dual clocked fifo with the incoming data. The write clock of FIFO is the output of a 4:1 clock multiplexer (implemented as a simple 4:1 mux using '?' operator although synthesizer shows a message like "clock mux found and protected"). Read clock is fixed at 200Mhz. A logic expects a particular pattern from input data. If the pattern is not found the logic switches the output of the clock mux and check again. Now you can imagine that the input register of FIFO is feed by the clock mux but in this case synth is not allowing the fast input register. I will try to put a register before the FIFO and see if this register allows the fast input register option to worl (as you said)

Ignore my post, as you're muxing 4 clocks. I thought you might be over-sampling with 4 registers clocked by different clocks. Different issues. Clock muxing is done upstream of the FF it's driving, and so placement of the FF does not depend on the mux. I'm guessing you're issue is that you're driving a RAM block in the FIFO, not a FF, and the RAM obviously can't be packed into the I/O cell. Adding the register would fix this.

Just a thought, but you may have better end results if you drive the clock from a pll and perform a pll reconfiguration instead of clock muxing

This Issue is resolved. As advised by dwh@ovro.caltech.edu and Rysc, placing a register prior to RAM allows fast input logic register to be placed by the synthesizer even though the clock is driven by the clock mux... Thanks to all of you

Great!