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Honored Contributor
Honored ContributorFalse triggering on dff?
I am using a Cyclone III starter kit with Quartus II v8.1 web edition. I am using library components to make a "one shot" with variable delay times in the msec range. There does not appear to be an...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- Of course it simulates fine with functional simulation. --- Quote End --- Yes. But a timing simulation most likely immediately reveals the design flaws. You'll realize, that both comparator outputs have glitches, that can trigger the DFF before reaching the equal count. You can either resync the comparator outputs by another DFF to the respective counter input clocks or use a preset down counter instead.
