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Altera_Forum
Honored Contributor
Honored ContributorFailed to route the following 1 signal(s)-- global signals
The device is : cyclone V 5CEFA9F31I7
The quartus version is 13.0 the fitter often failed and report the following message: error (170143): final fitting attempt was unsuccessful info (170138): failed to route the following 1 signal(s) info (170139): signal "ctl_nios:ctl_nios_i|ctl_sopc:ctl_sopc_i|ctl_sopc_control:control|data_out[0]~clkena0" info (170140): cannot fit design in device -- following 1 routing resource(s) needed by more than one signal during the last fitting attempt info (170141): routing resource internal device resource (x46_y46, i3) the reported signal is a global signal. it seems that one global signal can’t route, or conflict with other global signalsI have compiled the project many times. The fitter always failed to route one global signal, but not the same global signals. (The details shown at attached.) i don’t know why the fitter failed to route global signals(sometimes the fitter succeed). and how can i solve the problem?
5 Replies
Altera_ForumBy the looks of the number of clocks you have are stressing the global routing resources of the design.
The simplest for me to say (but hardest to implement) is to simply reduce the number of clocks in your design. It appears a difference between "Working" and "non-working" layouts is the number of regional clocks. Specifically, it appears the TX_DAC clocks gets split into two regions, versus one. I would start by locking down specific logic to specific regions in the design. (Especially associated with the regional clocks, or smaller clock domains). This should allow the results to be more repeatable at least. Pete- Altera_Forum--- Quote Start --- By the looks of the number of clocks you have are stressing the global routing resources of the design. The Device has 16 GCLK, My design have only used about 9 GCLK. I don't know why I stressed the global routing resources. Can I manually constrain the Global signal distribution to guide the fitter? Does it work?
- Altera_Forum
why do you need so many GCLKs? do you have logic generated clocks?
- Altera_Forum--- Quote Start --- why do you need so many GCLKs? do you have logic generated clocks? --- Quote End --- I only use 3 clock and 1 reset Global signal But quartus creat other Global signal: jtag clock, 3 syschronous reset signals(deassert) in qsys system, and 2-4 Global signal created by DDR2 SDRAM Controller with UniPHY. I do want to reduce the GCLKs, but quartus creat the so many GCLKs
- Altera_Forum
This is odd. Quartus fills up my global clock assignments as well, but never outright fails if I have extra clocks in the design.
Maybe you can get away with preventing a reset from using a global driver. I force a reset synchronizer to local routing by using this assignment (there's probably a better way): From To Assignment Name Value Enabled ...(remainder of path)...|altera_reset_synchronizer_int_chain_out Global Signal Off Yes
