Failed to route the following 1 signal(s)-- global signals

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why do you need so many GCLKs? do you have logic generated clocks?

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I only use 3 clock and 1 reset Global signal

But quartus creat other Global signal: jtag clock, 3 syschronous reset signals(deassert) in qsys system,

and 2-4 Global signal created by DDR2 SDRAM Controller with UniPHY.

I do want to reduce the GCLKs, but quartus creat the so many GCLKs