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edianannink's avatar
edianannink
Icon for New Contributor rankNew Contributor
1 year ago

FAILED to lock JTAG using JTAG primitive on Cyclone V

Dear FPGA engineers, We are trying to lock the JTAG using the Cyclone V JTAG primitive using the following guide: https://www.intel.com/content/www/us/en/docs/programmable/683269/current/lock-and-un...
Board Debug
Configuration
Programmable Logic Device
NurAiman_M_Intel's avatar
NurAiman_M_Intel
Icon for Super Contributor rankSuper Contributor
1 year ago

Hi,


As this forum post is similar to the IPS case you have created, I will continue to provide support through IPS and close this forum case.

Please refer to the IPS for further support.


Thank you.


Regards,

Aiman