Forum Discussion
Occasional Contributorfailed in creating agilex-f p-tile-pcie-avmm (RP X4) design example
Sorry, I overlook the dev kit setting. After putting the Agilex dev kit and generate the ED, the design files look bigger so I can't directly attach to here.
Here is the step to get the file:
Install Filezilla that can download from here:
https://filezilla-project.org/download.php?type=client
After installing, launch the tool and login as below:
Host: secureftp.intel.com
Username: tmp01481
Password: W@ng1234
Port 21.
You can see the zip file is located at the right of the window. Name = wang_ag.zip.
Frequent ContributorSorry, I overlook the dev kit setting. After putting the Agilex dev kit and generate the ED, the design files look bigger so I can't directly attach to here.
Here is the step to get the file:
Install Filezilla that can download from here:
https://filezilla-project.org/download.php?type=client
After installing, launch the tool and login as below:
Host: secureftp.intel.com
Username: tmp01481
Password: W@ng1234
Port 21.
You can see the zip file is located at the right of the window. Name = wang_ag.zip.
seanw_skhmsHi,
Downloaded the zip file without issue, thanks.
Learning the design, and have one question about the port assignment. The PCIe RP IP has four RP x4 bifurcation, and only the P0 core is exported in the design, which is assigned to PCIe lane#0-3 in the "pin planner". But according to PCIe IP document, UG-20237 table-57, the P0 is mapping to the PCIe lane#4-7 (instead of lane#0-3) in P-Tile 4x4 mode. I am so confused about the mapping between port# and core# by this example design.
Thanks.
Xiao
