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seanw_skhms's avatar
seanw_skhms
Icon for Occasional Contributor rankOccasional Contributor
5 years ago
Solved

failed in creating agilex-f p-tile-pcie-avmm (RP X4) design example

Quartus prime version 20.2.0 build 50 06/11/2020 SC pro edition, free 30 day license. Following the instructions shown in section 5.3, "generating the design example", in the document of "Intel FP...
  • BoonT_Intel's avatar
    BoonT_Intel
    5 years ago

    Sorry, I overlook the dev kit setting. After putting the Agilex dev kit and generate the ED, the design files look bigger so I can't directly attach to here.

    Here is the step to get the file:

    Install Filezilla that can download from here:

    https://filezilla-project.org/download.php?type=client

    After installing, launch the tool and login as below:

    Host: secureftp.intel.com

    Username: tmp01481

    Password: W@ng1234

    Port 21.

    You can see the zip file is located at the right of the window. Name = wang_ag.zip.

BoonT_Intel's avatar
BoonT_Intel
Icon for Frequent Contributor rankFrequent Contributor
5 years ago

Hi Sir,

I am attached the generated ED that based on your required setting.

  • seanw_skhms's avatar
    seanw_skhms
    Icon for Occasional Contributor rankOccasional Contributor
    5 years ago

    Hi,

    Downloaded the zip file, thank you very much for the help. I am learning it now.

    I saw that in the .ip file the the "current development kit" option is set to "none" instead of the agilex board. Any reason for doing it? For my understanding, the example design should target to a board in order to correctly assign the design IO pads locations. What should I know about this?

    Thanks,

    Xiao