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seanw_skhms's avatar
seanw_skhms
Icon for Occasional Contributor rankOccasional Contributor
5 years ago
Solved

failed in creating agilex-f p-tile-pcie-avmm (RP X4) design example

Quartus prime version 20.2.0 build 50 06/11/2020 SC pro edition, free 30 day license. Following the instructions shown in section 5.3, "generating the design example", in the document of "Intel FP...
  • BoonT_Intel's avatar
    BoonT_Intel
    5 years ago

    Sorry, I overlook the dev kit setting. After putting the Agilex dev kit and generate the ED, the design files look bigger so I can't directly attach to here.

    Here is the step to get the file:

    Install Filezilla that can download from here:

    https://filezilla-project.org/download.php?type=client

    After installing, launch the tool and login as below:

    Host: secureftp.intel.com

    Username: tmp01481

    Password: W@ng1234

    Port 21.

    You can see the zip file is located at the right of the window. Name = wang_ag.zip.

BoonT_Intel's avatar
BoonT_Intel
Icon for Frequent Contributor rankFrequent Contributor
5 years ago

By the way, are you able to generate the standalone IP? Also do you try to generate other IP's ED?

seanw_skhms's avatar
seanw_skhms
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

I am new in using the Quartus tool and the first practice is to generate the PCIe RP IP. So I have not do any other IP-DE yet.

regards,
Xiao

  • seanw_skhms's avatar
    seanw_skhms
    Icon for Occasional Contributor rankOccasional Contributor
    5 years ago

    I think the example design generation failure is caused by a bug in adding in the module of clock_crossing_bridge. The error message, at line#40 shown in "received_error_2.log" attached previously, shows,

    Error: add_fileset_file: No such file C:/Users/PC_LAB_FPGA1/AppData/Local/Temp/alt8499_1907179446840489927.dir/0001_intel_pcie_ptile_avmm_0_gen/ip/pcie_ed/pcie_ed_clock_crossing_bridge/altera_avalon_mm_clock_crossing_bridge_1920/synth/pcie_ed_clock_crossing_bridge_altera_avalon_mm_clock_crossing_bridge_1920_fdcxukq.v/pcie_ed_clock_crossing_bridge_altera_avalon_mm_clock_crossing_bridge_1920_fdcxukq.v

    The file name of "pcie_ed_clock_crossing_bridge_altera_avalon_mm_clock_crossing_bridge_1920_fdcxukq.v" is inserted two times in the file searching path.

    (But the message at line#38-39 shows that the other two rtl files, "*dc_fifo_1920_qcx4w5q.*", in the same folder were fetched correctly.)

    regards,
    Xiao