Forum Discussion
Occasional ContributorFacing Issue On Design Example: Intel Arria 10 FPGA Remote System Update via PCI Express*
Hi
I am trying to emulate the Design Example: Intel Arria 10 FPGA Remote System Update via PCI Express*. i am facing issue when we trying to download any application
can anyone help me on this?
Steps Followed by me
Step. 1 : Load Mater_Image jic file through onboard blaster - Success
Step 2: Reboot the dvk - Success - Four LED glows
Step 3: Copy driver, Install & run the driver - Success
Step 4: download application - Facing issue(PFA)
#######################################################################################
Flash Device ID: 1021bb20
Step1 : Do you want to download the application image to FLASH?
(Please input 'y' or 'n' to select, and press ENTER to go on):y
Step2 : Please input start and end address of application image downloaded to FLASH.
(You could get below information from *.map file, and input here.)
(Warning: Please use start address 0x0 if you are downloading factory image!!!)
START ADDRESS :0x04000000
END ADDRESS :0x5568FFF
Step3 : PLease input program file directory.
(For example: /home/rsu_over_pcie/user/ru_auto.rpd)
/home/jetson/GRL_C2V/A10_Flash/vel_image/app2c_auto.rpd
Info : Download application image into Flash, file size is 22450176 Bytes, start address is 0x4000000
Erasing EPCQ flash ...
################################################## 100%
Writing EPCQ flash ...
################################################## 100%
Reading back data from Flash ...
Warning : Flash data error at addr 0xc000000, expected data is 0x3a, but read data is 0x0
Warning : Checking stop due to read back data error
Step4 : Do you want to reconfig FPGA?
(Please input 'y' or 'n' to select, and press ENTER to go on):
Note: I am able perform Step4 (reconfig) With initial configuration(loaded using onboard blaster). Yes, able to reconfig different application
@Ryan_M_Intel
Thanks for the example design.
16 Replies
MIT_R_DHi,
Greetings!- When following the design example, is there any changes made in the design? If yes, which part?
- No change on design example. We are used same master_image - Is the design already programmed? It seems like it has but error at readback. If so, is the design functioning as intended?
- Write flash is completed. Readback error
- when we perform step 4(Do you want to reconfig FPGA?) with proper start address. its showing " Users Watchdog Timer timeout"
- The design not functioning as intended
Step4 : Do you want to reconfig FPGA?
(Please input 'y' or 'n' to select, and press ENTER to go on):y
(Warning: Please use start address 0x0 if you are reconfiguring to factory image!!!)
START ADDRESS :0x04000000
Info : Saving PCI control registers of the board.
-- Write 32bits 0 to bar 0, addr 2020004
-- Write 32bits 0 to bar 0, addr 2020008
-- Write 32bits 1 to bar 0, addr 2020010
-- Write 32bits 4000000 to bar 0, addr 202000c
-- Write 32bits 1 to bar 0, addr 2020018
Info : Restoring PCI control registers of the board.
-- Read 32bits ffffffff from bar 0, addr 2020000
Info : Altera Remote Update: Users Watchdog Timer timeout- When following the design example, is there any changes made in the design? If yes, which part?
NurAiman_M_IntelSuper Contributor
Hi,
Apologize for my previous response, but I need some clarification below:
- When following the design example, is there any changes made in the design? If yes, which part?
- Is the design already programmed? It seems like it has but error at readback. If so, is the design functioning as intended?
Regards,
Aiman
- NurAiman_M_Intel
Hi,
Thank you for contacting Intel community.
Per my understanding, you are using design example from below?
Also,
If your design is sensitive to the PCIe boot-up requirement, Intel recommends that you do not use the direct-to-application feature.
Intel recommends that you set a fixed start address and never update the start address during user mode. You should only overwrite an existing application configuration image when you have a new application image. This is to avoid the factory configuration image to be erased unintentionally every time you update the start address.
Can you try this? Let me know your feedback.
Regards,
Aiman
- MIT_R_D
Hi
Thanks for your response.Yes, I am using design example from below link
We are using same example design & driver.
"If your design is sensitive to the PCIe boot-up requirement, Intel recommends that you do not use the direct-to-application feature."
- can u please help how to disable direct-to-application feature?
Note: Configuration Mode is disabled from tool
"Intel recommends that you set a fixed start address and never update the start address during user mode"
- Yes, we are not changing start address and trying to update only application image
"You should only overwrite an existing application configuration image when you have a new application image. This is to avoid the factory configuration image to be erased unintentionally every time you update the start address."
- We are using master image jic file and updated through onboard blaster.
- We try to replace the application image(either 1 or 2) by using same master image(ru_auto) rpd file.We are getting read back data error error after 100% Erase & Write Completed
Flash Device ID: 1021bb20
Step1 : Do you want to download the application image to FLASH?
(Please input 'y' or 'n' to select, and press ENTER to go on):y
Step2 : Please input start and end address of application image downloaded to FLASH.
(You could get below information from *.map file, and input here.)
(Warning: Please use start address 0x0 if you are downloading factory image!!!)
START ADDRESS :0x04000000
END ADDRESS :0x5568FFF
Step3 : PLease input program file directory.
(For example: /home/rsu_over_pcie/user/ru_auto.rpd)
/home/jetson/GRL_C2V/A10_Flash/vel_image/app2c_auto.rpd
Info : Download application image into Flash, file size is 22450176 Bytes, start address is 0x4000000Erasing EPCQ flash ...
################################################## 100%
Writing EPCQ flash ...
################################################## 100%
Reading back data from Flash ...Warning : Flash data error at addr 0xc000000, expected data is 0x3a, but read data is 0x0
Warning : Checking stop due to read back data error
Step4 : Do you want to reconfig FPGA?
(Please input 'y' or 'n' to select, and press ENTER to go on):
