Forum Discussion
Altera_Forum
Honored Contributor
10 years agoHi,
you have to release the bridges from reset after loading the FPGA-Image. For that purpose you either have to generate a new preloader (u-boot SPL) with your current design or figure out the correct fpga2sdram_handoff. It can be gathered from the hps.xml inside the generated hps_isw_handoff folder in the project location. It should look like something like this:
<config name="F2SDRAM_COMMAND_PORT_USED" value="0x3"/>
<config name="F2SDRAM_READ_PORT_USED" value="0x1"/>
<config name="F2SDRAM_WRITE_PORT_USED" value="0x1"/>
<config name="F2SDRAM_RESET_PORT_USED" value="0x311"/>
You want to use in this case the 0x311 as fpga2sdram_handoff. Now you just have to boot the board to u-boot-stage, load the FPGA-Image and then type:
setenv fpga2sdram_handoff 0x311
run bridge_enable_handoff
After that the bridge should be released and you can go on doing further jobs... After project finishes, you would want to generate a preloader (u-boot SPL) with the correct values, then a simple
run bridge_enable_handoff
is enough, due to the hand over from preloader environment to u-boot environment. (And also because of that, a saveenv for the fpga2sdram_handoff will not work, it gets overwritten after reboot...!!!) I hope that helps