Forum Discussion

SDe_J's avatar
SDe_J
Icon for Occasional Contributor rankOccasional Contributor
3 months ago

F-tile CDR clock

Hello Intel forums

I have an Agilex 7 devkit that I'm working with. I'm still learning my way around the F-tile transceiver IPs and the Reference and System clocks PLL.

On the Agilex 7 devkit, refclks 8 & 9 on transceiver tile 12A are connected to the input of a SI5518 clock chip. I would like to make use of this connection to drive the SI5518. Can you tell me if the following are true:

  1. From what I understand, the connections of refclks 8 & 9 are restricted to the "out_cdrclk_i" ports of the Reference and System Clocks IP for that tile.
  2. I also understand that the "in_cdrclk_i" can only be connected to the "rx_cdr_divclk_link0" port of a transceiver IP on that tile.
  3. The frequency of "rx_cdr_divclk_link0" is given by the reference clock frequency divided by cdr_n_counter. In my case, this is 320MHz/12 = 26.666667 MHz. Assuming 1 & 2 are correct, I would need to configure the SI5518 to have this as the input frequency

Is "rx_cdr_divclk_link0" synchronized to the provided reference clock or to the clock recovered from the incoming data stream? To me, 'cdr' implies that it's related to the recovered clock, but I'm not sure if my understanding is correct.

Thank you for your assistance.
Kind Regards,
Sam

3 Replies

  • CheepinC_altera's avatar
    CheepinC_altera
    Icon for Regular Contributor rankRegular Contributor
    3 months ago

    Hi,

    Thank you for filing this case and sharing the details. I appreciate your patience. Please allow me some time to review the information, and I’ll get back to you as soon as possible.


  • SDe_J's avatar
    SDe_J
    Icon for Occasional Contributor rankOccasional Contributor
    3 months ago

    Hello CheePin,

    Have you been able to review the information?

    Kind Regards,
    Sam

  • CheepinC_altera's avatar
    CheepinC_altera
    Icon for Regular Contributor rankRegular Contributor
    2 months ago

    Hi Sam,


    Apologies for the delay, and I appreciate your patience.


    I understand you’ve been facing some challenges with clocking on the Agilex™ 7 F-Tile, and I’d like to help clarify things. To ensure we're aligned, I have a few quick checks and suggestions:


    1. Development Kit Reference

    Could you please confirm which specific Agilex 7 development kit you're using? A link to the product page would be helpful.

    For context, I’ve reviewed the schematics for both the Agilex I-Series Transceiver-SoC Development Kit and the Agilex 7 FPGA F-Series Development Kit, but I couldn’t locate any reference to the Si5518 clock chip. If you're using a different kit or a custom board, that might explain the discrepancy.


    2. Recommended Starting Point

    To get up and running quickly with the F-Tile, I recommend generating the PHY example design directly from the IP GUI. This example provides a solid reference for:


    IP configuration

    Clocking setup

    Module interconnections


    It’s a good way to understand how the pieces fit together before diving into customization.


    3. External CDR Clocking

    You mentioned using external clocks for CDR. Just to clarify — is there a specific reason you're opting for external CDR clocking?

    In most cases, the out_refclk_fgt_0 output from the System PLL can be used to drive the CDR reference clock for the Direct PHY. This is the typical setup unless your application has unique clocking requirements.


    Please let me know if you're seeing any issues with the example design generation or if there's a specific constraint driving your clocking approach. I’m here to help resolve this smoothly.


    Best regards,

    Chee Pin