F-tile CDR clock

Hi Sam,

Apologies for the delay, and I appreciate your patience.

I understand you’ve been facing some challenges with clocking on the Agilex™ 7 F-Tile, and I’d like to help clarify things. To ensure we're aligned, I have a few quick checks and suggestions:

1. Development Kit Reference

Could you please confirm which specific Agilex 7 development kit you're using? A link to the product page would be helpful.

For context, I’ve reviewed the schematics for both the Agilex I-Series Transceiver-SoC Development Kit and the Agilex 7 FPGA F-Series Development Kit, but I couldn’t locate any reference to the Si5518 clock chip. If you're using a different kit or a custom board, that might explain the discrepancy.

2. Recommended Starting Point

To get up and running quickly with the F-Tile, I recommend generating the PHY example design directly from the IP GUI. This example provides a solid reference for:

IP configuration

Clocking setup

Module interconnections

It’s a good way to understand how the pieces fit together before diving into customization.

3. External CDR Clocking

You mentioned using external clocks for CDR. Just to clarify — is there a specific reason you're opting for external CDR clocking?

In most cases, the out_refclk_fgt_0 output from the System PLL can be used to drive the CDR reference clock for the Direct PHY. This is the typical setup unless your application has unique clocking requirements.

Please let me know if you're seeing any issues with the example design generation or if there's a specific constraint driving your clocking approach. I’m here to help resolve this smoothly.

Best regards,

Chee Pin