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Honored Contributor
Honored ContributorExtremelly confused in Cyclone V Transceivers reconfiguration
Hello dear friends. I have a Cyclone V 5CSXFC6D6F31C8 chip. On PCB board, all 9 transceivers are connected to periphery and 1 reference clock (REFCLK1L) are connected to reference clock source ...
Altera_ForumHonored Contributor
Honored ContributorSo, i continue experiments: any configurations with channels count 2 and more will fails at fitter stage.
I try also external FPLL with 2-clock output, but it fails too because transceiver core need to be clocked from PHOUT output that drives only one clock. Can anybody say me what i do wrong?
