Forum Discussion
Gabe
New Contributor
4 years agoExternal Memory Controller
Hi, I can't seem to find this information anywhere. I need to design a PCB that has a DDR3 memory socket and and FPGA that would interact with the RAM memory plugged into the socket. Now my proble...
AdzimZM_Altera
Regular Contributor
4 years agoHi Gabe,
Thanks for clarifying your intentions.
Basically every memory timing must be configured according to the datasheet of the memory device.
Then the IP can be generated for the device.
If everything is configured correctly, the memory device should be working.
If the device is using the different memory timings, your design might encounter some errors such as timing violations or calibration error.
So I think generating each IP for your memory devices should be the best way to simulate your project.
I don't think that re-adjust the memory timings internally is a good way because you might be setting the value wrongly.
Regards,
Adzim