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Altera_Forum's avatar
Altera_Forum
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12 years ago

External Interface-like connection HPS to FPGA

Hello all,

I am trying to find a way to connect the HPS to the FPGA logic using an interface similar to those external interfaces which can be found in microcontrollers. Something with an address and data buses and the necessary control signals (CS, WE...). I intend to read and write to different configuration registers for my hardware components.

Until now I have been using the PIO Parallel unit but the ~500 LUTs and ~350 registers which are instantiated with every new node I add are way too much what I can spend. Also there I have no chance to detect new values I put at the output of the PIO unit from the FPGA logic unless I modify the automatically generated code manually.

Thank you very much in advance :)

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    Are you trying to connect to logic outside of your Qsys system? I'm assuming that's what you're asking. The easiest way is to "stub out" the Avalon bus. They may have a simple module to do this now, but last I checked, you have to create a very simple custom component with the component editor. No code, just go into the signals tab, create a new Avalon slave, and then define, data, address, read, write, and if necessary wait_req.

    It's not really an HPS-specific question, so you might find more info elsewhere in the forum. I'll look to see if I have any examples in the code I'm using on my Helio SoC board and will let you know if so.
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    Would really appreciate any input on this. I'm also working on mine with Arrow SocKit. Would like to be able to call FPGA modules and registers through HPS. Any examples would be greatly appreciated! newbie here. Thanks.

  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    In my design I have connected the "h2f_lw_axi_master" on the HPS to an "Avalon-MM bridge" component in QSYS. I then exported the slave side of the bridge to make the Avalon MM bridge available in my FPGA design.

    The Avalon-MM interface is very easy to use the signals that are exported to the slave side are: (outputs) Write, Read, Address, WriteData (inputs) ReadData, ReadDataValid, WaitRequest.

    There are also ByteEnable and BurstCount signals that you may want to use for your application.

    Basically, on a write transaction the master sets "WriteData" and "Address" when "Write" is high, your slave then does whatever you need with that data.

    On a read transaction the master sets "Read" and "Address" the slave is expected to provide "ReadData" for the corresponding read address and set "ReadDataValid". If the slave cannot process a transaction it sets "WaitRequest".

    I think you can cause the bus to "hang" if you fail to respond to a readrequest but your FPGA code shouldn't allow it to do that.

    Full details here http://www.altera.com/literature/manual/mnl_avalon_spec.pdf