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Altera_Forum
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12 years ago

External Interface-like connection HPS to FPGA

Hello all, I am trying to find a way to connect the HPS to the FPGA logic using an interface similar to those external interfaces which can be found in microcontrollers. Something with an addre...
Altera_Forum's avatar
Altera_Forum
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12 years ago

In my design I have connected the "h2f_lw_axi_master" on the HPS to an "Avalon-MM bridge" component in QSYS. I then exported the slave side of the bridge to make the Avalon MM bridge available in my FPGA design.

The Avalon-MM interface is very easy to use the signals that are exported to the slave side are: (outputs) Write, Read, Address, WriteData (inputs) ReadData, ReadDataValid, WaitRequest.

There are also ByteEnable and BurstCount signals that you may want to use for your application.

Basically, on a write transaction the master sets "WriteData" and "Address" when "Write" is high, your slave then does whatever you need with that data.

On a read transaction the master sets "Read" and "Address" the slave is expected to provide "ReadData" for the corresponding read address and set "ReadDataValid". If the slave cannot process a transaction it sets "WaitRequest".

I think you can cause the bus to "hang" if you fail to respond to a readrequest but your FPGA code shouldn't allow it to do that.

Full details here http://www.altera.com/literature/manual/mnl_avalon_spec.pdf