Extend Nios II bus for peripheral registers

Question

I'd like to extend the Nios II bus to access registers of Verilog modules that are outside of the QSys environment, similar to how an ARM processor accesses peripherals in the address space.  I have tried using the tri-state conduit master with 16-bit address and 16-bit data however this does not seem to be working.  I tried a simple test where I loopback the address onto the data input with a wire and do an IORD_16DIRECT in the C program but this has not given me the results I expect.  I am connecting the grant and request directly with a wire.  I am not sure if this is a problem.  Has anyone managed to get this to work?  Is there a special configuration that is needed?

altera_forum · Answer

Sure it works! Probably you connected it in a wrong way or your external module interface doesn't comply with bus signals.

altera_forum · Answer

Are there any examples of verilog modules that connect to the bus?

altera_forum · Answer

It looks like I misunderstood the Read Latency parameter.  I have set it to zero and that seems to behave as expected.

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Extend Nios II bus for peripheral registers

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