I am looking for example designs or tutorials showing how to communicate two Altera boards using simple protocols. The purpose is to see how the two devices interact by transmitting data back and forth and to check the transmission somehow. I am using two Altera Transceiver Signal Integrity Development Kit, Stratix IV GT (EP4S100G2F40I1) boards. Please help to advice if anyone knows such tutorials and examples. Also, any suggestions are highly appreciated. Thanks.

--- Quote Start --- I am looking for example designs or tutorials showing how to communicate two Altera boards using simple protocols. The purpose is to see how the two devices interact by transmitting data back and forth and to check the transmission somehow. I am using two Altera Transceiver Signal Integrity Development Kit, Stratix IV GT (EP4S100G2F40I1) boards. Please help to advice if anyone knows such tutorials and examples. Also, any suggestions are highly appreciated. --- Quote End --- What are you looking to test? The transceivers? At what data rate? What have you tried so far, eg., do you know how to configure the ALTGX and ALGX_RECONFIG components? What do you have in addition to the GT boards? Do you have break out cables? A synthesizer to provide a common clock between the boards? Cheers, Dave

Many thanks to Dave and please find my answers as following: 1-What are you looking to test? The transceivers? Yes, the main purpose is to to test transceivers, in particular with the Altera PHY IP cores. But besides these, I want to know how to create a design for two boards to communicate one another using some simpler protocol than the PHY IP cores. The data rate can be any not greater than 11.3Gbps 2-What have you tried so far? I have tried to test XCVR with On-chip debugging design examples provided by Altera. Then I created similar designs with Lowlatency and Custom PHY for various data rates using Qsys. However, I would like to have a 10Gbase-r PHY design and I could not create this in Qsys. I don't know if it is possible to create such design by using available components in Qsys. 3-Do you know how to configure the ALTGX and ALGX_RECONFIG components? I have general idea about the ALTGX and ALTGX_RECONFIG but have not ever used these as I want to try designing with Qsys first. 4-What do you have in addition to the GT boards? Do you have break out cables? A synthesizer to provide a common clock between the boards? I have SMA cables for physical connection between the two boards. For a synthesizer to provide the common clock, if you can make this clearer? Thanks.

--- Quote Start --- 1-What are you looking to test? The transceivers? Yes, the main purpose is to to test transceivers, in particular with the Altera PHY IP cores. But besides these, I want to know how to create a design for two boards to communicate one another using some simpler protocol than the PHY IP cores. The data rate can be any not greater than 11.3Gbps --- Quote End --- Unfortunately, there are lots of protocols, and lots of reasons for selecting a specific one. What is your final application? Are you going to be having FPGAs communicating with FPGAs, or do you need to interface with a 10G switch, or a Serial RapidIO switch, or SATA drives, or ... etc etc? --- Quote Start --- 2-What have you tried so far? I have tried to test XCVR with On-chip debugging design examples provided by Altera. Then I created similar designs with Lowlatency and Custom PHY for various data rates using Qsys. However, I would like to have a 10Gbase-r PHY design and I could not create this in Qsys. I don't know if it is possible to create such design by using available components in Qsys. --- Quote End --- What have you managed to test? Have you only tried these in hardware, or have you simulated them in Modelsim? --- Quote Start --- 3-Do you know how to configure the ALTGX and ALGX_RECONFIG components? I have general idea about the ALTGX and ALTGX_RECONFIG but have not ever used these as I want to try designing with Qsys first. --- Quote End --- You're doing things in reverse. Qsys is a convenience for connecting components. For a successful system design, you need to understand how these components work. For that understanding, you should start by configuring an ALTGX, an ALTGX_RECONFIG, create a reset controller, and then get them working in simulation and hardware. Use SignalTap II to trace that the hardware does what the simulation does (it doesn't, but the handbook tells you the difference - the key is being able to see and understand the differences). Since all other components are based on these two components, this will give you a fundamental understanding of how the interfaces work. --- Quote Start --- 4-What do you have in addition to the GT boards? Do you have break out cables? A synthesizer to provide a common clock between the boards? I have SMA cables for physical connection between the two boards. For a synthesizer to provide the common clock, if you can make this clearer? --- Quote End --- If one board uses a 156.25MHz reference that is actually a few kHz high, and the other board uses a reference that is a few kHz low, then one board will send data to the other faster than ideal. The clock-and-data recovery (CDR) in the receiver will track the higher frequency, however, if you use a FIFO to cross clock domains between the recovered clock and the local clock, you will eventually get a FIFO overrun (or underrun in the case of a slower transmitter). Protocols like 10G take care of this by having protocol codes that can be added or deleted. If you are implementing FPGA-to-FPGA communications, then the system becomes simpler if you use a synchronous reference. You can implement this reference using an external synthesizer and send a copy of the signal to each board, or you can use one of your boards as the clock source and the other can receive a clock from the first, and use it for clocking its receiver logic. To understand what I am talking about, configure an ALTGX transmitter with one reference frequency (156.25MHz + something), and an ALTGX receiver with another frequency (156.25MHz - something), and simulate it using Modelsim. If you don't know how to use Modelsim, its time to learn :) Ask questions, and I'll try to help. Cheers, Dave

Thanks Dave very much for your time and very detailed explanation. Let me describe briefly my final application. I am going to build a 10Gbps Ethernet Passive Optical Network (EPON) system where one FPGA will play a role as a center office device (OLT) and several other FPGAs will be customer premises (ONU). The boards will interface SFP+ modules. The design will consist of a physical layer protocol (probably by using Altera 10GBASE-R IP core) and my own implementation of MAC protocol (probably by modifying Altera 10GbE MAC IP core). The MAC for OLT device is different from that for ONUs. Therefore, I am trying to have physical layer first. I studied the Altera XCVR PHY IP Core User Guide and XCVR Architecture in Stratix IV manual. Then I tested the provided On-chip XCVR debugging examples in harware (not yet in Modelsim). However, 10GBASE-R is provided by Altera without a similar example for testing in hardware, so I tried to create that in Qsys with Avalon ultilities. With some knowledge from reading specs and Qsys, I though/hoped that I would create a complete 10GBASE-R design, then simulate it in Modelsim as well as test it on harware. I hoped that this top-down approach would help me understand the overview of my design more quickly. Moreover, as the PHY layer is provided as IP core, I do not really want to spend much time for this. I just want to know how to test this in hardware and know how to interface this with the other components in my final design. The major part of my project is to design the customized MAC sublayer. That is why I am doing things in reverse. I don't know if I am right when choosing this approach. Please give me some advice or/and suggest me better way(s) to reach my target application. For sure, to have a better understanding, I will learn to designs by configuring the ALTGX, RECONFIG,...like you recommended and learn to simulate in Modelsim. Also, I will learn to work with the SignalTap II and synthesizer soon. Again, thank you very much and look forward to your further advice.

--- Quote Start --- I am going to build a 10Gbps Ethernet Passive Optical Network (EPON) system where one FPGA will play a role as a center office device (OLT) and several other FPGAs will be customer premises (ONU). The boards will interface SFP+ modules. The design will consist of a physical layer protocol (probably by using Altera 10GBASE-R IP core) and my own implementation of MAC protocol (probably by modifying Altera 10GbE MAC IP core). The MAC for OLT device is different from that for ONUs. --- Quote End --- Ok, thanks for the description. --- Quote Start --- Therefore, I am trying to have physical layer first. I studied the Altera XCVR PHY IP Core User Guide and XCVR Architecture in Stratix IV manual. Then I tested the provided On-chip XCVR debugging examples in harware (not yet in Modelsim). However, 10GBASE-R is provided by Altera without a similar example for testing in hardware, so I tried to create that in Qsys with Avalon ultilities. With some knowledge from reading specs and Qsys, I though/hoped that I would create a complete 10GBASE-R design, then simulate it in Modelsim as well as test it on harware. --- Quote End --- My recommendation would be to take the XCVR debug example, which works, and simulate it. That'll allow you to probe a working design. I assume this is the 10GBASE-R IP you are looking at: http://www.altera.com/products/ip/iup/ethernet/m-alt-10gbase-r-pcs.html Note that 64/66B encoding is not supported in the Stratix IV hard-IP PCS, so it gets implemented in the fabric. You should synthesize to see how much logic the PCS layer is using. Given that the Stratix IV GT might not be a good use of resources, have you considered using a GX device with an external PHY? --- Quote Start --- I hoped that this top-down approach would help me understand the overview of my design more quickly. --- Quote End --- It might, if you also know how to simulate Qsys and create custom components. However, if you're introducing lots of new concepts, then you might actually be making the design more complicated. --- Quote Start --- Moreover, as the PHY layer is provided as IP core, I do not really want to spend much time for this. I just want to know how to test this in hardware and know how to interface this with the other components in my final design. The major part of my project is to design the customized MAC sublayer. That is why I am doing things in reverse. --- Quote End --- What you really should be doing then is getting the PHY working in the simulator so that you can simulate while working on your custom logic. Cheers, Dave

Example designs for communicating two Altera boards

49 Replies

Altera_Forum
Honored Contributor
14 years ago
Dear Dave,

I just found out that our NIC with SFP+ connector is the second one you found:
http://www.newegg.com/product/product.aspx?item=n82e16833120384
And it does only support Window Server among Windows OSs. We may have to decide whether:

1-Buy new NIC(s) that support Windows 7/vista or XP so that we can use Quartus II in Windows. But this seems to be an expensive choice.
2-Change to use Quartus II in Linux OS, but I did not have experience with this OS and this would be hard choice for me.
3-Keep using Windows Server 2008. But first, try to fix the issue for Qsys generation with On-chip memory cores. However, this is not a Quartus supported OS, so I don't know if I should try this direction.

Do you have any further advice?

I am more prone to the third option right now. Regarding the issue, you have suggested me to check the Java Runtime:

--- Quote Start ---

It looks like your script output stops right around the time Java is started. Perhaps Java on Windows Server 2008 is broken.

--- Quote End ---

I suspected that the current jre of Quartus has problems. So, I have installed newest Java 7 and replaced the content of C:\altera\11.1\quartus\bin64\jre64 with C:\Program Files\Java\jre7. But this does not help. If you have any further ideas about how to check and fix this issue?

Thank you very much.
PLMT
Altera_Forum
Honored Contributor
14 years ago
--- Quote Start ---

I just found out that our NIC with SFP+ connector is the second one you found:
http://www.newegg.com/product/product.aspx?item=n82e16833120384
And it does only support Window Server among Windows OSs. We may have to decide whether:

--- Quote End ---

That is unfortunate.

--- Quote Start ---

1-Buy new NIC(s) that support Windows 7/vista or XP so that we can use Quartus II in Windows. But this seems to be an expensive choice.

--- Quote End ---

You're kidding right? Your bosses went out and purchased $16,000 worth of Stratix GT kits before even determining that you could use them for your project ...

http://www.altera.com/products/devkits/altera/kit-stratix-iv-gt-si.html

and now they won't bother to spend $600 on a new NIC. Not only do you need the NIC, you also need the SFP+-to-SMA adapters.

Just buy the hardware. The time you are wasting now, and will waste trying to use an unsupported OS, will far exceed $600.

Cheers,
Dave
Altera_Forum
Honored Contributor
14 years ago
--- Quote Start ---
Just buy the hardware. The time you are wasting now, and will waste trying to use an unsupported OS, will far exceed $600.
--- Quote End ---

Thanks for your advice. So, I will no longer waste my time on fixing the problem.

How about the choice of using RedHat Enterprise Linux or SUSE Linux Enterprise with current NIC? Can you share some experience related to Altera software in these OSs?
Altera_Forum
Honored Contributor
14 years ago
--- Quote Start ---

How about the choice of using RedHat Enterprise Linux or SUSE Linux Enterprise with current NIC? Can you share some experience related to Altera software in these OSs?
--- Quote End ---
I use Centos 6.2. This is the 'community' version of RedHat 6.2. It works very well. I've used Centos for years, with previous versions of Quartus and Modelsim-ASE and SE, and have had no issues.

However, if you run Linux on your Windows Server 2008 machine, then you'll stop others from using it. Perhaps that is not an issue though.

I also use VirtualBox as a virtual machine manager. You can install Windows XP, Windows 7, Ubuntu, etc., as a VM client, and then the host OS running Centos can be used to give the USB-Blaster interface to the virtual machine. That way you can run the Board Test System (BTS) application under Windows XP to check your hardware. Using Windows 7 as the host OS does not support this (I'm not sure why, since Windows XP does).

Cheers,
Dave
Altera_Forum
Honored Contributor
14 years ago
--- Quote Start ---

I also use VirtualBox as a virtual machine manager. You can install Windows XP, Windows 7, Ubuntu, etc., as a VM client, and then the host OS running Centos can be used to give the USB-Blaster interface to the virtual machine.
--- Quote End ---

How about licensing? As I know, Altera does not support generation of licenses for virtual machine MAC addresses. How can I license my Quartus in an virtual environment?
Altera_Forum
Honored Contributor
14 years ago
--- Quote Start ---
How about licensing? As I know, Altera does not support generation of licenses for virtual machine MAC addresses. How can I license my Quartus in an virtual environment?
--- Quote End ---

In the case of using the VM to run the windows BTS application, licensing does not matter. You can install the full-edition in the VM so that the BTS application has access to the programmer and JTAG DLLs, but since you would not be synthesizing in the VM, you don't need to worry about the licensing.

Cheers,
Dave
Altera_Forum
Honored Contributor
14 years ago
on the licensing center you can actually generate companion licenses etc
Altera_Forum
Honored Contributor
14 years ago
--- Quote Start ---
In the case of using the VM to run the windows BTS application, licensing does not matter. You can install the full-edition in the VM so that the BTS application has access to the programmer and JTAG DLLs, but since you would not be synthesizing in the VM, you don't need to worry about the licensing.
--- Quote End ---

Thank you. So, I have one more option. I may try this. But first, I will discuss with my boss soon to have a decision.
Altera_Forum
Honored Contributor
14 years ago
--- Quote Start ---
1) Unzip your design

2) Opened the Qsys design and generated the system

3) Clicked on the files tab in the main GUI, and then clicked on the qsys_system.qsys and set it as the top-level entity (as described in the tutorial).

4) Synthesized the design.

There were no errors.
--- Quote End ---

As I mentioned before, I could generate the Qsys system using other PC (not the Windows server). Then, the compilation need to be done in the server because of the license issue. But, it was quite strange that the compilation took really long time to complete, more than 1 hour.
Can you tell me how long it takes for compiling in your PC?
Altera_Forum
Honored Contributor
14 years ago
--- Quote Start ---

Can you tell me how long it takes for compiling in your PC?
--- Quote End ---

No more than a few minutes. Windows XP, 2,2GHz, 3GB RAM. If you do not have much RAM, then your synthesis time will increase dramatically. I suspect that is your problem.

Cheers,
Dave

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Example designs for communicating two Altera boards

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