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ramsoffer_123's avatar
ramsoffer_123
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

evb cyclon v soc kit ddr3 throughput measurement is low

hi everyone, Im trying to read and write to ddr3 on the EVB cyclone v board. im using the ddr controller. i created read and write components to the controller through the avalon bus: ...
AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hi Ram,


Thank you for your feedback.


You can improve the efficiency of the memory controller by enabling the auto-precharge control option.

If you turn on Enable Auto-Precharge Control, you can instruct the controller to issue an auto-prechagre read or write command. The next time you access that bank, the access is faster because the controlled does not have to precharge the bank before activating the row that you want to access.


The address ordering also can improve the controller efficiency.

  • Choose Chip-Bank-Row-Col for random traffic.
  • Choose Chip-Row-Bank-Col for sequential traffic.
  • Choose Row-Chip-Bank-Col for sequential traffic and multiple chip selects.


From what I expect that the simulation result should be good, and the actual hardware may be slightly difference `because of the hardware connectivity and the memory device.


Regards,

Adzim