New ContributorEthernet Phy Fails to Link Between Marvell 88E111 PHY and Downstream port
I cannot seem to get a simple Marvell 88E111 PHY design to link to any external Ethernet port. Designing a prototype system with a Xilinx Ultra Scale FPGA. Embedded microprocessor only loaded with U-BOOT at this stage of development. Talking 1000BASE-X without clock, without auto negotiation to copper, (all of which I don't think should matter) except for the fact that I strapped the part interface as MIDO and U-BOOT only supports 2-wire out of the box. This leaves me welded to my configuration straps:
PHYADR [4:0] = 11110
ENA_PAUSE = 1
ANEG [3:0] 1111 = Auto Negotiate, advertise all capabilities, prefer slave
ENA_XC = 1, MDI crossover function is enabled
DIS_125 = 1, Disables 125MHz Clock
MODE [3:0] 0100 = SGMII without Clock with SGMII Auto-Neg to copper
DIS_FC = 0, Disables Fiber/Copper Auto Selection
DIS_SLEEP = 1, Disables Energy Detect
SEL_TWSI = 0, Select MDC/MDIO Interface
INT_POL = 1, INTn Signal is Active Low
75/50 Ohm = 0, 0 = 50 Ohm Termination for Fiber
2 mistakes I made (other than not including resistor options for the straps) is that I left TX_EN floating and assumed that the pins labeled TXD[7:0] were the transmit side (they are receive) of the unused GMII interface and left them floating RXD[7:0] it turns out are transmit, I pulled them up instead.
I have activity on the A pair and B pair to the downstream node. Some system I've plugged into flash the amber light, others show no lights at all.
The PHY is the bga version so reworking is major surgery. Since I don't know whether pulling up TX_EN and TXD[7:0] will fix the issue, I want to make sure I have exhausted all other avenues before punting.
Thoughts?
