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Altera_Forum
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16 years ago

Errors reading M9K dual port in Cyclone III

Hi, We are using four Megawizard generated dual ports in a 3C40F484C8. There are 128 locations, 24 bits wide, asynchronous write and read clocks. A common write_data and write_address bus goes to ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Hi,

The memory is instantiated like this

-----RAM 1---------------------------------------------------------------------

tx_mezz_ram_1 : tx_mezz_ram

port map(

wrclock => mezz_rx_clk_pll_out,

wraddress => write_addr,

data => write_data,

wren => wren,

rdclock => transmit_clock,

rdaddress => read_addr,

q => read_data0

);

The Megawizard vhd file is attached,

Regards