Errors reading M9K dual port in Cyclone III

No. I'm not doing that with Signal Tap, I re-run Quartus. This is half the problem really, adding a signal into SignalTap and the performance changes, so this is a good tip, thanks.

Perhaps the problem here is hold timing? The problem gets worse at lower temperatures, which suggests hold timing, and although the clock in the read domain is only 12MHz, hold timing is essentially independent of clock frequency. However the system is really very simple and passes timing analysis, both Classic and Timequest. It also does not fail if the memory is made of logic. Thanks for any input,

Regards