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Altera_Forum
Honored Contributor
17 years agoErrors reading M9K dual port in Cyclone III
Hi, We are using four Megawizard generated dual ports in a 3C40F484C8. There are 128 locations, 24 bits wide, asynchronous write and read clocks. A common write_data and write_address bus goes to ...
Altera_Forum
Honored Contributor
17 years agoHi, thanks for your reply. I do have SignalTap on write and read signals, although adding SignalTap to the read side quite often stops the error from occurring. When it does fail with SignalTap attached I can see the dual port read data corrupted. The read and write clocks are from 2 independent oscillators. I'm confident that the two sides of the memory use the two clocks correctly. It's the fact that the error occurs when the write data is active that concerns me, although I guess there could be some marginal timing on the read side that gets pushed into failing by some write side noise.
Thanks again for your reply, any other thoughts gratefully received, Regards,