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Altera_Forum's avatar
Altera_Forum
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14 years ago

Error:Connected system timestamp not found on target at expected base address.

Hi,

I'm fairly new to FPGA programming, please bear with me.

I tried to use Nios II and Quartus II 10.1 on Windows 7(64 bit) to programme a Altera DE2-70 board.

I basically followed these procedures:

1) Generate the SOPC which includes the Jtag Uart

2) add all files into the quartus II project and compile

3) Programme the board

4) Create a project including the application and bsp

5) Build the project

6) Run the project as Nios II hardware

Then it gives me the error:connected system id hash not found on target at expected base address

I tried to follow the posts from the forum and ignored the mismatch in Systemid and System timestamp. Then it gives me: downloading elf process failed.

If I click System ID Properties I get:

Expected system ID base address: 0x0 (as in SOPC)

Expected system ID:0x0

connected system id: not found

Expected system timestamp:1343399230 (as in SOPC)

connected system timestamp: not found

May I know what are the possible issues?

Any suggestions would be much appreciated .

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  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    Hi Daixiwen:

    Thank you for your reply. I am pretty sure that I have compored and configured the FPGA and used the _time_limited sof file.

    When I use the Nios2 command shell: nios2-terminal

    it shows:

    nios2-terminal:connected to hardware target using JTAG UART on cable

    nios2-terminal:"USB Blaster [USB]", device 1, instance 0

    nios2-terminal:<Use the IDE stop button or Ctrl+C to terminate>

    I guess the device is correctly connected and should be able to download the hardware program.

    But it still gives me the error about system id and timestamp mismatch.

    Is there any other possible bugs that could result in such error?

    Thank you!

    Jia Yang
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    You shouldn't ignore the mismatch in system id and timestamp. If there is a mismatch, it means there is a problem with the hardware configuration. Are you sure the project compiled correctly and that there were no errors when configuring the FPGA? Are you sure you selected the correct .sof file when programming the FPGA? If you use cores you don't have the license for, then the generated .sof file will have a _time_limited suffix, so be sure you select the right one.