Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Error: Too many output and bidirectional pins in I/O bank 2

Hi, everybody.

I am designing a new product on EP2C5Q208C8. In the design ,I use DDR sdram controller. so ,there are many sstl2 standard pins. But, I encounter the following error. how to run out?

thanks a lot.

Error: Too many output and bidirectional pins in I/O bank 2 assigned near VREF pin 192 (VREFGROUP_B2_N1) on device EP2C5Q208C8 -- no more than 5 output and bidirectional pins allowed near the VREF pin when voltage referenced pins are driving in, but there are potentially 6 pins driving out

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    The error means what it says. You are only allowed so many output pins near a VREF pin because of the potential noise effects on the VREF for the corresponding input pins. You need to either move one of the output pins to a different VREF group, or remove the input pin(s) from the group.

    Jake
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    jakobjones is basically right, there are however two cases, where the problem may simply overcome:

    - The error occurs, because you missed to specify correct output_enable_groups for the DQ and DQS pins. This may happen, if you didn't import all files generated by DDR controller Megawizard

    - The conflicting pins are fully static in normal operation and IO distance rules check can be disabled by specifying a toogle rate of 0 MHz.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    regarding the missing files that might not be imported, isn't it enough to add (all) the *.QIP files generated by the wizzards ? the qip files hold all informations needed to be included or added.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    when using DDR cores, there are also pin assignment Tcl scripts that should be run. in this case a .qip is not sufficient.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    well the FIR wizzard also generates TCL scripts that are included via QIP, i thought that adding the QIP generated by a wizzard is enough and quartus will do the required actions if a QIP is added. in that case run the tcl file.

    hmmm, what should be the correct way for automatically running tcl scripts that come from a wizzard if those functionality is added into a design ?