Error placing clock pin with Clock Control Block

FvM,

You are correct, multiplexing of the GX transceiver PLL input reference clocks is handled via the ALT2GXB_RECONFIG megacore.

However, I also use the reference clock for other functions within the FPGA core. Specifically in this case, the two reference clocks are two different frequencies used to generate different broadcast video standards using the GX transceivers.

In addition to this, I also use the reference clocks directly to generate a video sync (black burst, tri-level, etc.) signal via an external DAC. I need to switch between the two clocks in order to generate different standards.

Anyway, I've changed the code to just do the muxing in an LCELL and placing the output on a global buffer.

Jake